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NXP Semiconductors /LPC408x_7x /LCD /LE

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Interpret as LE

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LED0RESERVED0 (LEE)LEE 0RESERVED

Description

Line End Control register

Fields

LED

Line-end delay. Controls Line-end signal delay from the rising-edge of the last panel clock, LCD_DCLK. Program with the number of LCDCLK clock periods minus 1.
RESERVED

Reserved. Read value is undefined, only zero should be written.
LEE

LCD Line end enable. 0 = LCD_LE disabled (held LOW). 1 = LCD_LE signal active.
RESERVED

Reserved. Read value is undefined, only zero should be written.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data